Subsequent to fabrication of wafers having many integrated circuits formed thereon, it is a common practice to test the functionality and electrical characteristics of those integrated circuits while still in wafer form. That is, well-known semiconductor processes are used to perform a variety of operations on a wafer, culminating in the formation of a plurality of integrated circuits, which are typically cut apart so that individual integrated circuits may be put into protective packages, or otherwise incorporated into products. However, in order to prevent the packaging, or other use, of integrated circuits that may have manufacturing defects, the wafer is coupled to one or more test systems to verify that the integrated circuits contained in that wafer, perform according to the specifications associated with those integrated circuits.
Conventionally, electrical connection between a test system and the individual integrated circuits, sometimes referred to as die, is made via a probe card. These probe cards provide a first mechanism to electrically interface, or connect, with a test system, and a second mechanism to physically touch and electrically connect with the very small contact pads exposed at a top surface of each integrated circuit. This second mechanism typically consists of probes, sometimes referred to as probe needles, that must be precisely shaped, aligned, and the tips of which must be positioned in a co-planar manner so that the probe tips all touch the contact pads of an integrated circuit without being short of the target pad, and without driving too deeply into the pad.
Subsequent to testing the individual integrated circuits on the wafer, those integrated circuits that have successfully passed testing, are packaged and then re-tested. This re-testing of the packaged integrated circuits, sometimes referred to as “final test”, may be used to determine whether the assembly operations of packaging have resulted in a part that does not function properly, or may be used for conveniently testing the integrated circuits in environmentally challenging settings, such as for example, elevated temperatures. Operating, or testing, an integrated circuit at elevated temperature is sometimes referred to as burn-in. Such burn-in testing may identify integrated circuits that do not function according their specifications. Unfortunately, detecting failures after an integrated circuit has been packaged results in higher costs for a manufacturer than if such a failure could have been detected while the integrated circuit was still in wafer form.
What is needed are methods and apparatus for wafer-level, that is pre-singulation, testing of the integrated circuits on a wafer that is operated within a user defined temperature range.